Staff Verification Engineer

As Staff Verification Engineer at Riverlane, you’ll own verification across block, subsystem, and multi-FPGA designs, collaborating with hardware and software teams to deliver verified, high-performance systems. You’ll define and execute the verification strategy from early design through full system validation, ensuring reliability and quality. The role places you at the heart of our fast-growing QEC effort, shaping the product's robustness and impact. This is a hands-on position with a clear emphasis on scalable verification and cross-functional influence.

• annual bonus plan
• private medical insurance
• life insurance
• contributory pension
• equity
• learning budget and growth programme

• Own strategy and execution for block-level, subsystem, and multi-FPGA designs
• Develop scalable UVM-based testbenches across multiple FPGAs and configurations
• Drive verification with focus on risk, coverage, and system-level behaviour
• Make pragmatic trade-offs to maintain world-class quality while innovating
• Collaborate with hardware designers and embedded software engineers and define verification strategy from design to system validation

• Strong hands-on expertise in SystemVerilog and UVM
• Experience verifying complex FPGA designs and integrations
• Proven ability to debug across RTL, simulation, and hardware
• Commercial experience in functional verification including verification planning and strategy ownership
• Exposure to programming languages such as C, C++, and Python
• Proactive, independent worker with good scope definition abilities
• Collaborative with excellent communication and feedback skills

• collaborative
• strong communication
• ability to work with ambiguity
• SystemVerilog
• UVM
• FPGA verification