Verification Engineer Platforms Team

As a Senior Verification Engineer at Codasip UK, you will define and lead verification strategies for secure, CHERI-enabled architectures. You’ll build scalable testbenches and drive coverage across IP and system levels, collaborating with hardware and software teams. You’ll own verification plans, track progress, and close coverage gaps to ensure robust ASIC/FPGA validation. You join a cross-functional, innovation-driven Platform team shaping the next era of secure computing.

• Define verification strategies, plans, and coverage goals from architectural specs
• Develop and maintain scalable IP- and system-level verification environments using SystemVerilog/UVM
• Execute simulations, root-cause analysis, and support FPGA-based validation
• Develop functional coverage models and SystemVerilog Assertions (SVA) and automate verification flows
• Collaborate cross-functionally with hardware designers and software engineers, manage estimation and risk reporting

• Solid hands-on IP- and system-level verification with SystemVerilog and UVM
• Constrained-random testing, simulation, and gate-level verification
• Proven ability to create verification plans, functional coverage, and assertions (SVA)
• Programming/automation in SystemVerilog, Python, C++, or Rust; Linux scripting
• Experience with Git, SVN, and CI tools to support automated regression flows
• Strong problem-solving in computer systems and processor architecture; end-to-end ownership of verification deliverables

• Collaborative mindset
• initiative and curiosity
• strong communication across multidisciplinary teams
• SystemVerilog
• UVM
• constrained-random testing